The present invention generally relates to semiconductor integrated circuits, and more particularly to an interface circuit provided between a compound semiconductor (GaAs, for example) logic circuit and a bipolar transistor circuit.
Recently, GaAs logic LSIs have widely been used in the field of signal processing circuits in data processing devices. GaAs logic LSIs consume a small amount of power and operate at high speeds. On the other hand, emitter coupled logic (ECL) circuits composed of bipolar transistors have also been used widely. Thus, there is a need to provide an interface circuit between the GaAs logic LSI and the ECL circuit. Such an interface circuit matches the output level of an output transistor in the GaAs logic LSI with the input level of an input transistor of the ECL circuit.
FIG. 1 illustrates a related interface circuit (GaAs/ECL interface circuit) provided between a GaAs logic circuit and an ECL circuit. The interface circuit shown in FIG. 1 is driven by two different power sources having voltages Vss1 (=-2.0 V) and Vss2 (=-1.5 V) with respect to a ground potential GND. As shown, the interface circuit has an input buffer circuit 1, a level shift circuit 2, a super buffer circuit 3, an output transistor T00, an output level adjustment circuit 4 and an output terminal resistor RL. The input buffer circuit 1 has transistors T21 and T22. The level shift circuit 2 has transistors T23 and T24, and a diode DR21. The super buffer circuit 3 has a high speed driving ability and comprises of transistors T25, T26, T27 and T28. The output level adjustment circuit 4 is made up of transistors T29 and T30.
The transistors T21, T24, T25, T29 and T30 are formed of depletion type (normally ON type) Schottky barrier (metal semiconductor) field effect transistors having GaAs compound semiconductors as major components. The transistors T22, T23, T26, T27, T28 and T00 are formed of enhancement type (normally OFF type) Schottky barrier field effect transistors.
The source of the transistor T00, that is the terminal connected to, the output terminal resistor RL connected to an output terminal OUT, has a function of matching the output level of the interface circuit shown in FIG. 1 with the input level of an ECL circuit 5. Normally, the output terminal resistor RL has a resistance equal to 50 ohms, and also functions to prevent the occurrence of the reflection of a signal wave from the ECL circuit 5. The output level adjustment circuit 4 serves as a current source, and increases the low level of the output terminal OUT by, for example, 100 mV.
The ECL circuit 5 has a differential circuit, comprising emitter-coupled npn bipolar transistors Q1 and Q2, and resistors R1 and R2 provided for the setting of the operation of the ECL circuit 5. The collectors of the bipolar transistors Q1 and Q2 are respectively coupled, though the resistors R1 and R2, to a high-voltage power supply line having a high power supply voltage V.sub.CC. The emitters of the bipolar transistors Q1 and Q2 are connected to receive a low power supply volta V.sub.EE. The collector of the bipolar transistor Q2 forms an output terminal OUT' of the ECL circuit 5. A reference voltage Vref is applied to the base of the bipolar transistor Q2.
When an input logic signal having a high (H) level is applied to the gate of the transistor T22 of the input buffer circuit 1, an output logic signal having a high (H) level is output to the output terminal OUT. Then, the output logic signal is applied to the base B of the transistor Q1 of the ECL circuit 5. On the other hand, when the input logic signal has a low (L) level, the output logic signal obtained at the output terminal OUT has a low (L) level, which corresponds to a voltage increased by 100 mV from the voltage Vss1 due to the function of the output level adjustment circuit 4.
Another related circuit is shown in FIG. 2, in which those parts which are the same as those shown in FIG. 1 are given the same reference numerals. A normal buffer circuit 6 is substituted for the super buffer circuit 3 shown in FIG. 1. The normal buffer circuit 6 has a depletion type Schottky barrier field effect transistor T31, and an enhancement type Schottky barrier field effect transistor T32. The output signal of the normal buffer circuit 6 rises more slowly than that of the super buffer circuit 3. That is, the super buffer circuit 3 rises its output signal rapidly, so that it can be applied to a specific application, such as a clock signal. The circuit shown in FIG. 2 operates in the same way as that shown in FIG. 1.
However, the circuits shown in FIGS. 1 and 2 have disadvantages, which will be described with reference to FIGS. 3A and 3B. FIG. 3A is a graph showing the relationship between an output current (Iout [A]) passing through the output terminal resistor RL and an output voltage (VO [V]) obtained at the output terminal OUT. In FIG. 3A, a line A is a load resistance curve of the output terminal resistor RL (equal to 50 ohms), and a curve B is a load resistance curve of the transistor T29. It will be noted that the transistor T29 functions as a constant-current source and thus its impedance is approximately a few kiloohms (e.g., 8 kiloohms). Vte0 (=0 V), Vte1 (=0.1 V), Vte2 (=0.2 V), Vte3 (=0.3 V) and Vte4 (=0.4 V) are threshold voltages of samples of the output transistor T00. That is, the threshold voltages of the samples are different from each other by 100 mV. The output transistor T00 operates at a cross point of the lines A and B. It can be seen from the graph of FIG. 3A that when the output terminal OUT is maintained at the low level, the output impedance of the interface circuit shown in FIG. 1 or FIG. 2 is extremely high, as compared with that of the resistance of the output terminal resistor RL. If the interface circuit shown in FIG. 1 or FIG. 2 processes a high-speed signal having a frequency equal to or higher than 100 MHz, signal wave reflection will take place and thus the output signal waveform will deteriorate.
Further, as shown in FIG. 3B, the output voltages are much different from each other, due to the respective, different threshold voltages of the various different output transistors T00 which may be used. Such variations in the output voltage will cause a malfunction of the ECL circuit 5.
The inventor made an improvement in the circuits shown in FIGS. 1 and 2 in order to reduce the above-mentioned disadvantages. FIG. 4 shows an improvement in the circuit shown in FIG. 1 made by the inventor. A super buffer circuit 3A in FIG. 4 is substituted for the super buffer circuit 3 shown in FIG. 1. An enhancement type Schottky barrier field effect transistor 33 is added to the circuit of the super buffer circuit 3 shown in FIG. 1. The gate and drain of the transistor 33 are mutually connected, and the source thereof is connected to the drain of the transistor T28. The transistor 33 functions to increase the gate voltage of the output transistor T00 by the value of the threshold voltage of the transistor 33, providing a reduced output impedance of the interface circuit shown in FIG. 4 relatively to that FIGS. 1 and 2. The improvement shown in FIG. 4 does not use the output level adjustment circuit 4 shown in FIG. 1. A level conversion circuit employing a transistor similar to the transistor T33 is disclosed in Japanese Laid-Open Patent Publication No. 1-137827.
FIG. 5A illustrates the output impedance characteristic of the improved circuit shown in FIG. 4. A line B1 in FIG. 5A shows the output impedance (differential output resistance) of the improved interface circuit shown in FIG. 4 when the output terminal is maintained at the low level. It can be seen from FIG. 4 that the line A crosses the curves of the threshold voltages Vte0-Vte4 at substantially flat portions thereof and the output impedance is approximately 22 ohms for Vte2=0.2 V, which is approximately 1/40 of the output impedance of the circuit shown in FIG. 1.
FIG. 5B illustrates the output level characteristic of the improved interface circuit shown in FIG. 4. It can be seen from FIG. 5B that variations in the output signal, resulting from differences of the respective threshold voltages of the differing output transistors T00, can be reduced.
However, it is still desired to further suppress the variations in the output signal obtained at the output terminal OUT due to the different threshold voltages.